The present invention relates to improving the switching performance of an integrated circuit, and more particularly to a logic circuit employing clocked pass transistor and complementary pass transistor logic.
Pass transistor logic is one of the oldest logic techniques used in forming integrated circuits. Prior to the advent of complementary metal-oxide semiconductor (CMOS) technology currently popular in integrated circuit fabrication, pass transistor logic had been used in n-channel metal-oxide semiconductor (NMOS) circuits. Pass transistor logic was subsequently implemented in CMOS technology circuits. For example, CMOS pass transistor logic has been applied in microprocessors and other circuits. Comparisons have been made between pass transistor logic and standard CMOS logic for a variety of different applications and power supply voltages.
Static pass transistor logic circuits of the type shown in FIGS. 1-2 have been used in CMOS technology and integrated circuits, for example, in the design of microprocessors and other structures. However, static pass transistor logic circuits suffer from a common problem: there is a threshold voltage drop at the input across a pass transistor. As illustrated in FIG. 1, if the input voltage source 28 is VDD at a logical xe2x80x9c1xe2x80x9d or high logic state, then the voltage at a node 34 (the input to the inverter 22) will rise only to VDDxe2x88x92VTN, where VTN is the threshold voltage of the transistor 26. In addition, the rise time required for the node 34 to reach this voltage (VDDxe2x88x92VTN) is theoretically infinite, since the NMOS pass transistor 26 has a final state which theoretically has infinite resistance.
This problem is exacerbated if, as shown in FIG. 2, the output of one pass transistor 32 is used to drive the gate of another transistor 26. In the circuit shown in FIG. 2, the voltage at node 34 (the input to the inverter 22) will charge only to VDDxe2x88x922VTN. This result is unacceptable in low power supply circuits and therefore design rules preclude such a configuration.
Various techniques have been used to overcome these problems. One technique is the use of level restore circuits, examples of which are illustrated in FIGS. 3-4. Referring to FIG. 3, a level restore circuit 30 is illustrated, including a pass transistor 26 and level restore transistor 38, in which the output of the inverter 22 is fed back to control a PMOS level restore transistor 38. If the input to the inverter 22 at the node 34 is switching high, then the output of the inverter 22 is switching low, thus driving the gate of the PMOS level restore transistor 38 to pull up the input to the inverter 22 at the node 34. This is a positive feedback circuit which tends to latch the input high regardless of how slowly the original input signal was rising. In this manner, the level restore circuit 30 overcomes the threshold voltage drop at the input to the inverter 22. The level restore circuit 40 shown in FIG. 4 is essentially equivalent to the level restore circuit 30 of FIG. 3, except that an additional inverter 44 is used to drive the gate of the PMOS level restore transistor 42 to pull up the input to the inverter 22 at the node 34.
Another problem plaguing pass transistor logic circuits is signal propagation delay. For a plurality of pass transistor stages connected in series, each stage including a pass transistor circuit and an inverter, when the logic state of the first pass transistor circuit changes state, a chain reaction ensues in which every output changes state in sequence. For example, FIG. 9 illustrates a plurality of pass transistor circuits 26 and inverters 22 connected in series. The noted chain reaction causes a long signal delay through the chain, wasting energy and causing high power dissipation. Concerns about propagation delay of pass transistor logic spurred the development of prediction logic circuits attached to each inverter in the chain. However, incorrect predictions may lead to the combination of an input and an output of an inverter at a same logic state, which is not a stationary or stable condition for such a circuit.
Accordingly, there is a strong desire and need to improve the switching performance of integrated circuits using logic that overcomes the voltage drop and propagation delay problems of pass transistor logic.
A logic circuit and associated method are provided to improve the switching performance of integrated circuit devices. Clocked pass transistor logic is combined with precharge circuitry, and the output nodes of clocked inverters receiving the output of the pass transistor circuits are precharged low. The precharging reduces signal propagation delays and can significantly increase the performance of switching in integrated circuits employing pass transistors.
The logic circuit includes a pass transistor logic circuit; a clocked inverter circuit including a CMOS transistor pair having a gate of a first transistor coupled to a gate of a second transistor, the coupled gates being coupled to an output of the pass transistor logic circuit, and a first source/drain region of the first transistor coupled to a first source/drain region of the second transistor, the coupled first source/drain regions being coupled to an output of the clocked inverter circuit, wherein a second source/drain region of the first transistor is coupled to a first potential terminal. The logic circuit further includes a clocking transistor coupled between the second transistor and a second potential terminal and having a gate coupled to a first clocking signal and a precharge transistor coupled between the clocked inverter output and the second potential terminal and having a gate coupled to a second clocking signal.
In another aspect of the invention, switching performance is improved by allowing only low to high transitions at the output of the clocked inverter circuit. The output of the clocked inverter circuit is precharged low. If the output of the pass transistor logic connected to the input of the clocked inverter is attempting to switch high and thus the output of the inverter is attempting to switch low, then the output of the clocked inverter will simply remain low at the precharged state. If the output of the pass transistor logic is attempting to switch low and thus the output of the inverter is attempting to switch high, then the output of the clocked inverter will transition from the low precharge to a high state quickly through low resistance PMOS transistors in the clocked inverter circuit.
In another aspect of the invention, a clocking transistor and a precharge transistor are used to assist in precharging the output of the inverter circuit while avoiding unstable circuit conditions. The clocked inverter circuit includes one or more clocking transistors which couple the inverter circuit to ground only during periods in which the inverter output is not being precharged. The gate of the clocking transistor is controlled by a first clocking signal, and the gate of the precharge transistor is controlled by a second clocking signal, each of the first and second clocking signals having a first state (e.g., low) during a precharge phase and then transitioning to a second state (e.g., high) during an inverter operation phase. The first and second clocking signals are complementary signals so that during the precharge phase, the precharge transistor is gated (e.g., high state) while the clocking transistor is not gated (e.g., low state), and therefore the output of the inverter circuit is precharged low and the inverter is not enabled. During a subsequent operation phase, precharging ceases, the inverter is enabled and the output of the pass transistor circuit controls the output of the inverter circuit. The output of the inverter circuit is evaluated during the operation phase.